Semiconductor devices, such as large scale integrated circuits (LSI), are manufactured by alternately stacking an insulation layer and a conductive layer on a semiconductor substrate. Generally, a layer formed on the semiconductor substrate through a chemical vapor deposition (CVD) process, or the like is patterned according to an etching process, thereby stacking layers on the semiconductor substrate. During is the etching process, plasma generated by various devices, such as a parallel plate plasma plasma source, an inductively-coupled plasma (ICP) plasma source, and an electron cyclotron resonance (ECR) plasma source is used.
Recently, in semiconductor devices including a semiconductor element, such as a metal oxide semiconductor (MOS) transistor, a 3-dimensional structure is required in terms of high integration. Here, a configuration of a MOS transistor having a 3-dimensional structure will be simply described.
FIGS. 12 and 13 are exterior perspective views of a semiconductor device 101 including a MOS transistor having a 3-dimensional structure. FIG. 12 shows a conductive layer 109, to be described later, before being etched, and FIG. 13 shows the conductive layer 109 after being etched. Referring to FIGS. 12 and 13, the semiconductor device 101 includes a plurality of protrusions 104 that are conductive and extend perpendicularly to a main surface 103 of a semiconductor substrate (wafer) 102. Each of the protrusions 104 extends in a direction indicated by an arrow XII of FIG. 12. A source region and a drain region are formed along a length direction of each protrusion 104, wherein the conductive layer 109 as shown in FIG. 13 is sandwiched therebetween.
An insulation layer 105 formed of SiO2 film is formed on the semiconductor substrate 102. Also, a thin SiO2 film 106 is formed as a gate oxide film on a channel region disposed between the source region and the drain region so as to cover the protrusion 104. Here, since the SiO2 film 106 constituting a gate oxide film is formed to cover the protrusions 104, a high step XI in a layer-stacking direction exists between a top surface 107 of the protrusions 104, and a surface 108.
Next, the conductive layer 109 formed of polysilicon (polycrystalline silicon) is formed to cover the SiO2 film 106. Then, the conductive layer 109 of polysilicon is patterned by using a resist 110 as a mask, and etched so as to remove a predetermined region of the conductive layer 109 as shown in FIG. 13. The remaining conductive layer 109 is a gate electrode. As such, the MOS transistor having a 3-dimensional structure is formed on the semiconductor substrate 102. Here, an etching residue 111 remains on sides of each protrusion 104.
Accordingly, when the etching process is performed on the conductive layer 109 of poly-silicon having the high step XI, the etching process may be performed in two operations having different processing conditions, as disclosed in Japanese Laid-Open Patent Publication No. hei 9-69511. Here, the etching process may be performed by a is plasma processing apparatus, such as the ICP plasma source, where HBr gas or Cl2 gas with a very small amount of O2 is generally used as an etching gas.
According to Japanese Laid-Open Patent Publication No. hei 9-69511, the etching process may be performed on the conductive layer 109 of poly-silicon in two operations including a main etching process and an over etching process. FIG. 14 is a graph showing a relationship between an etching area ratio and a etching selectivity during an etching process. In FIG. 14, the horizontal axis indicates the etching area ratio (%), and the vertical axis indicates the etching selectivity (poly-silicon/SiO2).
Here, the etching area ratio is a ratio of an area S2 of exposed poly-silicon to be etched with respect to the total sum of the area S2 and an area S3 of SiO2 exposed from the bottom layer of the poly-silicon through an etching process. In other words, an etching area ratio in FIG. 12 is 100, since there exists only an area S1 of exposed poly-silicon to be etched, and the area S3 of the exposed SiO2 is 0. Also, when all SiO2 is exposed as the poly-silicon is etched out, the etching area ratio is 0. The etching selectivity is a ratio of an etching rate of poly-silicon when an etching rate of SiO2 is 1.
Referring to FIG. 14, when SiO2 is not exposed as in FIG. 12, the main etching process is performed in a low etching selectivity so as to obtain an accurate shape. As the main etching process is performed, the area S2 of a portion to be etched decreases, and the exposed area S3 of SiO2 increases. As a result, the etching residue 111 remains on the sides of each protrusion 104 as shown in FIG. 13. Here, when the etching process is performed on the etching residue 111, a reaction product, such as SiBr, generated by the etching process is activated, and the reaction product deteriorates the etching selectivity. When the etching process is performed in a low etching selectivity, the thin SiO2 film 106 having a large exposed area, specifically the top surface 107 of the thin SiO2 film 106 which exists on the top surfaces of the protrusions 104, may be easily damaged. Accordingly, as shown in FIG. 14, during the over etching process, the etching process needs to be performed in a high etching selectivity, for example, in a etching selectivity of 50 or above.
When the etching process is performed in two steps as described above, the etching process needs to be performed in different conditions, and thus number of operations increases, thereby decreasing the efficiency of manufacturing a semiconductor device.